The present invention relates to a semiconductor testing apparatus and a DC testing apparatus constituting the semiconductor testing apparatus, and particularly, it relates to a DC testing apparatus suitable for testing a flash memory.
In a conventional DC testing apparatus which constitutes a semiconductor testing apparatus, a test pattern is input for each of the pins of a device under test (DUT) such as a flash memory, and the resultant output is compared with an expected value for detecting whether the DUT is defective or not.
The following will simply describe one example of the DC testing apparatus in the conventional semiconductor testing apparatus with reference to FIG. 4.
The example of the conventional DC testing apparatus comprises a sequencer 11, an analog/digital converter (ADC) 12, and an arithmetic/logical unit (ALU) 13.
When an AD start signal is input from a pattern generator (PG) 2 of a semiconductor testing apparatus, the sequencer 11 outputs a start signal and a timing signal in turn.
When the start signal is input from the sequencer 11, the ADC 12 measures an output of a DUT 3, which is input a test pattern generated by the PG 2. Here, a flash memory, which is tested, is shown as an example of the DUT 3.
Also, when the timing signal is input from the sequencer 11, the ALU 13 outputs an output voltage of the ADC 12 as a measurement value, and outputs a result of comparing this output voltage value with an expected value as a PASS/FAIL signal. This expected value is a value which is set at the ALU 13 beforehand, and which is to be output when the flash memory is normal.
When the output voltage value of the ADC 12 matches the expected value, the ALU 13 outputs the PASS signal, and when it does not match, the ALU 13 outputs the FAIL signal. This PASS/FAIL signal is typically given in the state of a binary signal and is represented by, for example, xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d.
On the other hand, the ALU 13 outputs the output voltage value as an output voltage of the DUT 3 directly, which is analog/digital-converted in the ADC 12.
The PASS/FAIL signal output from the ALU 13 is input to the PG 2.
The test patterns, which are input from the PG 2 to the DUT 3, are changed one by one in accordance with the PASS/FAIL signal input from the ALU 13. At the time of each change operation, either of the two test patterns is selected according to whether the PASS or FAIL signal is given. That is, one of the branches of the test pattern is sequentially selected.
For each selected test pattern, an AD start signal is input from the PG 2 to the sequencer 11. Then, the ADC 12 measures an output of DUT 3 to which the test pattern is input, and new PASS/FAIL signals are output from the ALU 13 one after another.
Thus, each time the test is conducted, a plurality of test patterns is input for each of the DUT pins and the AD start signal is output. This AD start signal is output as many times as, for example, a few tens of times for each test.
However, the output voltage value given as a measurement value from the ALU has conventionally been only an output voltage value measured corresponding to a test pattern when the last AD start signal is output. That is, conventionally, it has been impossible to directly confirm an actual output value of the DUT against each of the test pattern except the last test pattern.
Also, sometimes an output signal is judged that an output voltage value converted by the ADC matches an expected value by the ALU even when actually it is only barely satisfied with an allowable range of an expected value or is actually abnormal because it matches the expected value accidentally. In such a case, although naturally the FAIL signal indicative of abnormality must be output, actually the PASS signal indicative of normality may be output. Thus, it would deteriorate the reliability of the DC test.
In view of the above, it is an object of the present invention to provide a DC measuring apparatus and a semiconductor testing apparatus that can measure an output voltage value placed from a DUT corresponding to a test pattern which is given each time when the AD start signal is input for easy debugging a test program and a test pattern of DC tests.
In order to achieve this object, a DC testing apparatus in claim 1 of the present invention comprises a sequencer for outputting a start signal, a timing signal, a write-in signal, and a clock signal sequentially, when an AD start signal for each test pattern is input from a pattern generator for generating the test pattern to be input to a device under test (DUT); an analog/digital converter for measuring an output of said DUT to which the test pattern is input, when said start signal is input; an arithmetic/logical unit (ALU) for outputting an output voltage value of said analog/digital converter as a measurement value, when said timing signal is input, and for outputting a result of comparing said output voltage value with an expected value to said pattern generator as a PASS/FAIL signal; an address counter for updating an address value to be output, when said clock signal is input; and a history memory for storing said measurement value in an address indicated by said address value, when said write-in signal is input.
According to such a constitution, each time when the AD start signal is input to the sequencer, the write-in signal and the clock signal are output following the start signal and the timing signal. This clock signal is used to update an address value in the address counter. Further, the write-in signal is used to store a voltage value output in the history memory. Therefore, each time when the AD start signal is given, the address of the history memory, which stores each output voltage value, is updated.
Therefore, according to the present invention, it is possible to individually retain each output voltage value for each AD start signal. As a result, it is possible to individually measure each voltage value output from the DUT against a test pattern for each AD start signal.
Thus, according to the present invention, because each voltage value output from the DUT against a test pattern for each AD start signal can be measured, it is possible to analyze in detail the output of the DUT for each of the test patterns. As a result, even when the PASS/FAIL signal comes in the PASS signal, it is possible to detect such a case that the measurement value hardly matched the allowable range of an expected value or that it accidentally matched the expected value but is actually decided to be abnormal.
By then modifying the test pattern or the expected value based on the result of the detection, it is possible to reduce the probability of the PASS signal indicative of normality being output in such a case that the FAIL signal indicative of abnormality should be output originally. Therefore, the reliability of the DC test would be improved.
Furthermore, because the output of the DUT for each test pattern can be discussed in detail, based on the discussion result, the DUT itself can be improved at its development stage. Therefore, by using a DC testing apparatus of the present invention at the stage of developing a DUT such as a flash memory, it is possible to contribute to the development of the improved DUT in performance.